1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same, and particularly to a semiconductor device having a static random access memory (SRAM) memory cell and a method for manufacturing the same.
2. Description of the Related Art
As semiconductor memory devices, e.g. a dynamic random access memory (DRAM) and a static random access memory (SRAM) are widely used.
Several types of the SRAM memory cell are known. For example, an SRAM memory cell of the smallest configuration is composed of two p-channel metal-oxide-semiconductor (PMOS) transistors and four n-channel metal-oxide-semiconductor (NMOS) transistors, i.e. total six MOS field effect transistors (MOSFETs).
The SRAM is advantageous in the following features over a semiconductor memory device, such as the DRAM, requiring a capacitor exclusively for the memory and so on in addition to a transistor: favorable affinity for a pure logic process; simplified peripheral circuitry due to no necessity for refresh operation for stored data, which is required in the DRAM; and high-speed accessibility. Thus, the SRAM is widely used as a memory device that is required to have high speed and simplicity and has a comparatively-low capacity, such as a cache memory and a memory of a portable terminal.
FIG. 20A is an equivalent circuit diagram of an SRAM memory cell having six MOSFETs.
This SRAM memory cell has load transistors LTr1 and LTr2 as two PMOS transistors, driver transistors DTr1 and DTr2 as two NMOS transistors, and transfer transistors TTr1 and TTr2 as two NMOS transistors.
The drain of each of the load transistor LTr1 and the driver transistor DTr1 is connected to one memory node ND, and the gate of each of these transistors is connected to the other memory node ND. The source of the load transistor LTr1 is connected to a supply voltage Vcs, and the source of the driver transistor DTr1 is connected to a reference potential. By this load transistor LTr1 and the driver transistor DTr1, one CMOS inverter that has the other memory node ND as its input and has the one memory node ND as its output is formed.
The drain of each of the load transistor LTr2 and the driver transistor DTr2 is connected to the other memory node ND, and the gate of each of these transistors is connected to the one memory node ND. The source of the load transistor LTr2 is connected to the supply voltage Vcs, and the source of the driver transistor DTr2 is connected to the reference potential. By this load transistor LTr2 and the driver transistor DTr2, one CMOS inverter that has the one memory node ND as its input and has the other memory node ND as its output is formed.
The input and output of the CMOS inverter composed of the load transistor LTr1 and the driver transistor DTr1 and the output and input of the CMOS inverter composed of the load transistor LTr2 and the driver transistor DTr2 are connected to each other in a ring manner, and thereby one memory circuit is formed.
The gate of the transfer transistor TTr1 is connected to a word line WL, the drain thereof is connected to a bit line BL, and the source thereof is connected to the one memory node ND. The gate of the transfer transistor TTr2 is connected to the word line WL, the drain thereof is connected to a complementary bit line BL, and the source thereof is connected to the other memory node ND.
The potential of the bit line BL is set to an external supply voltage Vdd. The potential of the cell-inside power supply Vcc is set to Vcs. The cell-inside power supply is connected via the load transistors LTr1 and LTr2 to the memory nodes ND and ND. For simplification of the power supply circuit for example, the external power supply is typically equalized to the internal power supply (Vdd=Vcs).
As a related art, to address unstable operation of an SRAM due to the size reduction thereof, a method of employing different gate insulating film thicknesses for the MOSFETs included in an SRAM memory cell has been proposed.
For example, Japanese Patent Laid-open Nos. Hei 6-295999 and Hei 8-37243 disclose a method in which the thickness of the gate insulating films of the transfer transistors TTr1 and TTr2 is set larger than that of the gate insulating films of the driver transistors DTr1 and DTr2 to thereby enhance the static noise margin (SNM) characteristic of the SRAM and strengthen the resistance against noise from the bit line BL.
However, this method involves a problem that the lowering of the transistor capability of the transfer transistors TTr1 and TTr2 is caused and therefore the lowering of the read speed and the deterioration of the write margin are caused.
In recent years, an SRAM dual-power-supply technique in which the cell-inside voltage is set higher than the bit line voltage (Vdd<Vcs) has been proposed (refer to e.g. Implementation of the CELL Broadband Engine™ in a 65 nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6 GHz at 1.3V, J. Pille et al., 2007 IEEE International Solid-State Circuits Conference, pp. 322-324). Setting Vcs higher can increase the amplitude of the inverters formed based on the driver transistors DTr1 and DTr2 and the load transistors LTr1 and LTr2, and setting Vdd lower can reduce noise from the external.
This can avoid the lowering of the read speed and the deterioration of the write margin, and can stabilize the SRAM operation.
However, although the SRAM dual-power-supply technique (Vdd<Vcs) allows the stabilization of the SRAM operation, it involves increase in the standby leakage due to increase in the leakage from the gate insulating film, and the deterioration of the reliability of the gate insulating film. The mechanism thereof will be described below.
FIG. 20B is a schematic sectional view for explaining three leakage paths that exist across the gate insulating film of each transistor.
A gate insulating film 101 is formed on a semiconductor substrate 100, and a gate electrode 102 is formed thereon. Sidewall spacers 103 are formed on both the sides of the gate electrode. In the partial portions of the semiconductor substrate 100 on both the sides of the gate electrode 102, a source region 104S and a drain region 104D are formed. In this manner, a MOSFET is formed.
This configuration involves three kinds of leakage: leakage “a” that occurs between the gate electrode and the channel part when the transistor is in the on-state; leakage “b” that occurs across the overlapping part between the source and the gate electrode both when the transistor is in the on-state and when it is in the off-state; and leakage “c” that occurs across the overlapping part between the drain and the gate electrode both when the transistor is in the on-state and when it is in the off-state.
A discussion will be made below about the leakage in the standby state of the SRAM when the SRAM dual-power-supply technique (Vdd<Vcs) is used for these three kinds of leakage.
The standby state refers to the inactive state in which the memory nodes ND/ND are fixed at High/Low or Low/High (“High” corresponds to the state of the high voltage Vcc=Vcs, and “Low” corresponds to the state of the low voltage Vss=0). In the standby state, the transfer transistors TTr1 and TTr2 are in the off-state, i.e., the word line WL connected to the gates of the transfer transistors TTr1 and TTr2 is at 0 V, and the bit line BL is generally fixed at Vdd. This standby state occupies most part of the SRAM operation.
FIG. 21 is a schematic diagram for explaining the leakage in the standby state in which the memory node ND is at High (Vcc=Vcs) and the memory node ND is at Low (Vss=0). For three paths of the respective transistors, the place across which a potential difference arises and leakage occurs is indicated by an arrowhead. In FIG. 21, the dashed-line arrowhead indicates the place across which a potential difference of Vcs arises, and the full-line arrowhead indicates the place across which a potential difference of Vdd arises.
In this manner, due to the use of the dual power supply (Vdd<Vcs), the potential difference applied to the gate insulating film differs from part to part, which causes increase in the standby leakage and the deterioration of the reliability and resistance of the gate insulating film.
As a countermeasure against the increase in the standby leakage due to the dual power supply, a method in which the thickness of the gate insulating film is designed corresponding to the high voltage Vcs will be available. However, this thickness design is redundant for the place to which only the low voltage Vdd is applied, and thus leads to the lowering of the operating speed of the SRAM.